\doxysubsubsubsection{UART Hardware Flow Control }
\hypertarget{group___u_a_r_t___hardware___flow___control}{}\label{group___u_a_r_t___hardware___flow___control}\index{UART Hardware Flow Control@{UART Hardware Flow Control}}
\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t___hardware___flow___control_gae0569001c06b7760cd38c481f84116cf}{UART\+\_\+\+HWCONTROL\+\_\+\+NONE}}~0x00000000U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t___hardware___flow___control_ga6d5dad09c6abf30f252084ba0f8c0b7d}{UART\+\_\+\+HWCONTROL\+\_\+\+RTS}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7c5d6fcd84a4728cda578a0339b4cac2}{USART\+\_\+\+CR3\+\_\+\+RTSE}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t___hardware___flow___control_ga352f517245986e3b86bc75f8472c51ea}{UART\+\_\+\+HWCONTROL\+\_\+\+CTS}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa125f026b1ca2d76eab48b191baed265}{USART\+\_\+\+CR3\+\_\+\+CTSE}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t___hardware___flow___control_ga7c91698e8f08ba7ed3f2a0ba9aa27d73}{UART\+\_\+\+HWCONTROL\+\_\+\+RTS\+\_\+\+CTS}}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7c5d6fcd84a4728cda578a0339b4cac2}{USART\+\_\+\+CR3\+\_\+\+RTSE}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa125f026b1ca2d76eab48b191baed265}{USART\+\_\+\+CR3\+\_\+\+CTSE}})
\end{DoxyCompactItemize}


\doxysubsubsubsubsection{Detailed Description}


\label{doc-define-members}
\Hypertarget{group___u_a_r_t___hardware___flow___control_doc-define-members}
\doxysubsubsubsubsection{Macro Definition Documentation}
\Hypertarget{group___u_a_r_t___hardware___flow___control_ga352f517245986e3b86bc75f8472c51ea}\index{UART Hardware Flow Control@{UART Hardware Flow Control}!UART\_HWCONTROL\_CTS@{UART\_HWCONTROL\_CTS}}
\index{UART\_HWCONTROL\_CTS@{UART\_HWCONTROL\_CTS}!UART Hardware Flow Control@{UART Hardware Flow Control}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_HWCONTROL\_CTS}{UART\_HWCONTROL\_CTS}}
{\footnotesize\ttfamily \label{group___u_a_r_t___hardware___flow___control_ga352f517245986e3b86bc75f8472c51ea} 
\#define UART\+\_\+\+HWCONTROL\+\_\+\+CTS~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa125f026b1ca2d76eab48b191baed265}{USART\+\_\+\+CR3\+\_\+\+CTSE}}}

Clear To Send \Hypertarget{group___u_a_r_t___hardware___flow___control_gae0569001c06b7760cd38c481f84116cf}\index{UART Hardware Flow Control@{UART Hardware Flow Control}!UART\_HWCONTROL\_NONE@{UART\_HWCONTROL\_NONE}}
\index{UART\_HWCONTROL\_NONE@{UART\_HWCONTROL\_NONE}!UART Hardware Flow Control@{UART Hardware Flow Control}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_HWCONTROL\_NONE}{UART\_HWCONTROL\_NONE}}
{\footnotesize\ttfamily \label{group___u_a_r_t___hardware___flow___control_gae0569001c06b7760cd38c481f84116cf} 
\#define UART\+\_\+\+HWCONTROL\+\_\+\+NONE~0x00000000U}

No hardware control \Hypertarget{group___u_a_r_t___hardware___flow___control_ga6d5dad09c6abf30f252084ba0f8c0b7d}\index{UART Hardware Flow Control@{UART Hardware Flow Control}!UART\_HWCONTROL\_RTS@{UART\_HWCONTROL\_RTS}}
\index{UART\_HWCONTROL\_RTS@{UART\_HWCONTROL\_RTS}!UART Hardware Flow Control@{UART Hardware Flow Control}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_HWCONTROL\_RTS}{UART\_HWCONTROL\_RTS}}
{\footnotesize\ttfamily \label{group___u_a_r_t___hardware___flow___control_ga6d5dad09c6abf30f252084ba0f8c0b7d} 
\#define UART\+\_\+\+HWCONTROL\+\_\+\+RTS~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7c5d6fcd84a4728cda578a0339b4cac2}{USART\+\_\+\+CR3\+\_\+\+RTSE}}}

Request To Send \Hypertarget{group___u_a_r_t___hardware___flow___control_ga7c91698e8f08ba7ed3f2a0ba9aa27d73}\index{UART Hardware Flow Control@{UART Hardware Flow Control}!UART\_HWCONTROL\_RTS\_CTS@{UART\_HWCONTROL\_RTS\_CTS}}
\index{UART\_HWCONTROL\_RTS\_CTS@{UART\_HWCONTROL\_RTS\_CTS}!UART Hardware Flow Control@{UART Hardware Flow Control}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_HWCONTROL\_RTS\_CTS}{UART\_HWCONTROL\_RTS\_CTS}}
{\footnotesize\ttfamily \label{group___u_a_r_t___hardware___flow___control_ga7c91698e8f08ba7ed3f2a0ba9aa27d73} 
\#define UART\+\_\+\+HWCONTROL\+\_\+\+RTS\+\_\+\+CTS~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7c5d6fcd84a4728cda578a0339b4cac2}{USART\+\_\+\+CR3\+\_\+\+RTSE}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa125f026b1ca2d76eab48b191baed265}{USART\+\_\+\+CR3\+\_\+\+CTSE}})}

Request and Clear To Send 